532 lines
11 KiB
C
532 lines
11 KiB
C
/* LIBPIKA - The PIKA Library
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* Copyright (C) 1995-1997 Peter Mattis and Spencer Kimball
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*
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* This library is free software: you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 3 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library. If not, see
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* <https://www.gnu.org/licenses/>.
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*/
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/*
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* x86 bits Copyright (C) Manish Singh <yosh@gimp.org>
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*/
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/*
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* PPC CPU acceleration detection was taken from DirectFB but seems to be
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* originating from mpeg2dec with the following copyright:
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*
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* Copyright (C) 1999-2001 Aaron Holtzman <aholtzma@ess.engr.uvic.ca>
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*/
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#include "config.h"
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#include <string.h>
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#include <signal.h>
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#include <setjmp.h>
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#include <glib.h>
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#include "pikacpuaccel.h"
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/**
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* SECTION: pikacpuaccel
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* @title: pikacpuaccel
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* @short_description: Functions to query and configure CPU acceleration.
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*
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* Functions to query and configure CPU acceleration.
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**/
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static PikaCpuAccelFlags cpu_accel (void) G_GNUC_CONST;
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static gboolean use_cpu_accel = TRUE;
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/**
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* pika_cpu_accel_get_support:
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*
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* Query for CPU acceleration support.
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*
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* Returns: #PikaCpuAccelFlags as supported by the CPU.
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*
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* Since: 2.4
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*/
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PikaCpuAccelFlags
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pika_cpu_accel_get_support (void)
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{
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return use_cpu_accel ? cpu_accel () : PIKA_CPU_ACCEL_NONE;
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}
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/**
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* pika_cpu_accel_set_use:
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* @use: whether to use CPU acceleration features or not
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*
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* This function is for internal use only.
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*
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* Since: 2.4
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*/
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void
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pika_cpu_accel_set_use (gboolean use)
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{
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use_cpu_accel = use ? TRUE : FALSE;
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}
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#if defined(ARCH_X86) && defined(USE_MMX) && defined(__GNUC__)
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#define HAVE_ACCEL 1
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typedef enum
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{
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ARCH_X86_VENDOR_NONE,
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ARCH_X86_VENDOR_INTEL,
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ARCH_X86_VENDOR_AMD,
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ARCH_X86_VENDOR_CENTAUR,
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ARCH_X86_VENDOR_CYRIX,
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ARCH_X86_VENDOR_NSC,
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ARCH_X86_VENDOR_TRANSMETA,
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ARCH_X86_VENDOR_NEXGEN,
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ARCH_X86_VENDOR_RISE,
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ARCH_X86_VENDOR_UMC,
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ARCH_X86_VENDOR_SIS,
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ARCH_X86_VENDOR_HYGON,
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ARCH_X86_VENDOR_UNKNOWN = 0xff
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} X86Vendor;
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enum
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{
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ARCH_X86_INTEL_FEATURE_MMX = 1 << 23,
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ARCH_X86_INTEL_FEATURE_XMM = 1 << 25,
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ARCH_X86_INTEL_FEATURE_XMM2 = 1 << 26,
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ARCH_X86_AMD_FEATURE_MMXEXT = 1 << 22,
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ARCH_X86_AMD_FEATURE_3DNOW = 1 << 31,
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ARCH_X86_CENTAUR_FEATURE_MMX = 1 << 23,
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ARCH_X86_CENTAUR_FEATURE_MMXEXT = 1 << 24,
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ARCH_X86_CENTAUR_FEATURE_3DNOW = 1 << 31,
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ARCH_X86_CYRIX_FEATURE_MMX = 1 << 23,
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ARCH_X86_CYRIX_FEATURE_MMXEXT = 1 << 24
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};
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enum
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{
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ARCH_X86_INTEL_FEATURE_PNI = 1 << 0,
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ARCH_X86_INTEL_FEATURE_SSSE3 = 1 << 9,
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ARCH_X86_INTEL_FEATURE_SSE4_1 = 1 << 19,
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ARCH_X86_INTEL_FEATURE_SSE4_2 = 1 << 20,
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ARCH_X86_INTEL_FEATURE_AVX = 1 << 28
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};
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#if !defined(ARCH_X86_64) && (defined(PIC) || defined(__PIC__))
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#define cpuid(op,eax,ebx,ecx,edx) \
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__asm__ ("movl %%ebx, %%esi\n\t" \
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"cpuid\n\t" \
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"xchgl %%ebx,%%esi" \
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: "=a" (eax), \
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"=S" (ebx), \
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"=c" (ecx), \
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"=d" (edx) \
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: "0" (op))
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#else
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#define cpuid(op,eax,ebx,ecx,edx) \
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__asm__ ("cpuid" \
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: "=a" (eax), \
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"=b" (ebx), \
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"=c" (ecx), \
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"=d" (edx) \
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: "0" (op))
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#endif
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static X86Vendor
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arch_get_vendor (void)
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{
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guint32 eax, ebx, ecx, edx;
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union{
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gchar idaschar[16];
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int idasint[4];
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}id;
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#ifndef ARCH_X86_64
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/* Only need to check this on ia32 */
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__asm__ ("pushfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"movl %0,%1\n\t"
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"xorl $0x200000,%0\n\t"
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"pushl %0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl %0\n\t"
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"popfl"
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: "=a" (eax),
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"=c" (ecx)
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:
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: "cc");
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if (eax == ecx)
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return ARCH_X86_VENDOR_NONE;
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#endif
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cpuid (0, eax, ebx, ecx, edx);
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if (eax == 0)
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return ARCH_X86_VENDOR_NONE;
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id.idasint[0] = ebx;
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id.idasint[1] = edx;
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id.idasint[2] = ecx;
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id.idaschar[12] = '\0';
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#ifdef ARCH_X86_64
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if (strcmp (id.idaschar, "AuthenticAMD") == 0)
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return ARCH_X86_VENDOR_AMD;
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else if (strcmp (id.idaschar, "HygonGenuine") == 0)
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return ARCH_X86_VENDOR_HYGON;
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else if (strcmp (id.idaschar, "GenuineIntel") == 0)
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return ARCH_X86_VENDOR_INTEL;
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#else
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if (strcmp (id.idaschar, "GenuineIntel") == 0)
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return ARCH_X86_VENDOR_INTEL;
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else if (strcmp (id.idaschar, "AuthenticAMD") == 0)
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return ARCH_X86_VENDOR_AMD;
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else if (strcmp (id.idaschar, "HygonGenuine") == 0)
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return ARCH_X86_VENDOR_HYGON;
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else if (strcmp (id.idaschar, "CentaurHauls") == 0)
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return ARCH_X86_VENDOR_CENTAUR;
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else if (strcmp (id.idaschar, "CyrixInstead") == 0)
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return ARCH_X86_VENDOR_CYRIX;
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else if (strcmp (id.idaschar, "Geode by NSC") == 0)
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return ARCH_X86_VENDOR_NSC;
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else if (strcmp (id.idaschar, "GenuineTMx86") == 0 ||
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strcmp (id.idaschar, "TransmetaCPU") == 0)
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return ARCH_X86_VENDOR_TRANSMETA;
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else if (strcmp (id.idaschar, "NexGenDriven") == 0)
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return ARCH_X86_VENDOR_NEXGEN;
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else if (strcmp (id.idaschar, "RiseRiseRise") == 0)
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return ARCH_X86_VENDOR_RISE;
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else if (strcmp (id.idaschar, "UMC UMC UMC ") == 0)
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return ARCH_X86_VENDOR_UMC;
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else if (strcmp (id.idaschar, "SiS SiS SiS ") == 0)
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return ARCH_X86_VENDOR_SIS;
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#endif
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return ARCH_X86_VENDOR_UNKNOWN;
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}
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static guint32
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arch_accel_intel (void)
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{
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guint32 caps = 0;
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#ifdef USE_MMX
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{
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guint32 eax, ebx, ecx, edx;
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cpuid (1, eax, ebx, ecx, edx);
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if ((edx & ARCH_X86_INTEL_FEATURE_MMX) == 0)
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return 0;
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caps = PIKA_CPU_ACCEL_X86_MMX;
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#ifdef USE_SSE
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if (edx & ARCH_X86_INTEL_FEATURE_XMM)
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caps |= PIKA_CPU_ACCEL_X86_SSE | PIKA_CPU_ACCEL_X86_MMXEXT;
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if (edx & ARCH_X86_INTEL_FEATURE_XMM2)
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caps |= PIKA_CPU_ACCEL_X86_SSE2;
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if (ecx & ARCH_X86_INTEL_FEATURE_PNI)
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caps |= PIKA_CPU_ACCEL_X86_SSE3;
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if (ecx & ARCH_X86_INTEL_FEATURE_SSSE3)
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caps |= PIKA_CPU_ACCEL_X86_SSSE3;
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if (ecx & ARCH_X86_INTEL_FEATURE_SSE4_1)
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caps |= PIKA_CPU_ACCEL_X86_SSE4_1;
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if (ecx & ARCH_X86_INTEL_FEATURE_SSE4_2)
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caps |= PIKA_CPU_ACCEL_X86_SSE4_2;
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if (ecx & ARCH_X86_INTEL_FEATURE_AVX)
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caps |= PIKA_CPU_ACCEL_X86_AVX;
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#endif /* USE_SSE */
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}
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#endif /* USE_MMX */
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return caps;
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}
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static guint32
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arch_accel_amd (void)
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{
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guint32 caps;
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caps = arch_accel_intel ();
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#ifdef USE_MMX
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{
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guint32 eax, ebx, ecx, edx;
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cpuid (0x80000000, eax, ebx, ecx, edx);
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if (eax < 0x80000001)
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return caps;
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#ifdef USE_SSE
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cpuid (0x80000001, eax, ebx, ecx, edx);
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if (edx & ARCH_X86_AMD_FEATURE_3DNOW)
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caps |= PIKA_CPU_ACCEL_X86_3DNOW;
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if (edx & ARCH_X86_AMD_FEATURE_MMXEXT)
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caps |= PIKA_CPU_ACCEL_X86_MMXEXT;
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#endif /* USE_SSE */
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}
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#endif /* USE_MMX */
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return caps;
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}
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static guint32
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arch_accel_centaur (void)
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{
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guint32 caps;
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caps = arch_accel_intel ();
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#ifdef USE_MMX
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{
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guint32 eax, ebx, ecx, edx;
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cpuid (0x80000000, eax, ebx, ecx, edx);
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if (eax < 0x80000001)
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return caps;
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cpuid (0x80000001, eax, ebx, ecx, edx);
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if (edx & ARCH_X86_CENTAUR_FEATURE_MMX)
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caps |= PIKA_CPU_ACCEL_X86_MMX;
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#ifdef USE_SSE
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if (edx & ARCH_X86_CENTAUR_FEATURE_3DNOW)
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caps |= PIKA_CPU_ACCEL_X86_3DNOW;
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if (edx & ARCH_X86_CENTAUR_FEATURE_MMXEXT)
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caps |= PIKA_CPU_ACCEL_X86_MMXEXT;
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#endif /* USE_SSE */
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}
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#endif /* USE_MMX */
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return caps;
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}
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static guint32
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arch_accel_cyrix (void)
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{
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guint32 caps;
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caps = arch_accel_intel ();
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#ifdef USE_MMX
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{
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guint32 eax, ebx, ecx, edx;
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cpuid (0, eax, ebx, ecx, edx);
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if (eax != 2)
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return caps;
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cpuid (0x80000001, eax, ebx, ecx, edx);
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if (edx & ARCH_X86_CYRIX_FEATURE_MMX)
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caps |= PIKA_CPU_ACCEL_X86_MMX;
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#ifdef USE_SSE
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if (edx & ARCH_X86_CYRIX_FEATURE_MMXEXT)
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caps |= PIKA_CPU_ACCEL_X86_MMXEXT;
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#endif /* USE_SSE */
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}
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#endif /* USE_MMX */
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return caps;
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}
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#ifdef USE_SSE
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static jmp_buf sigill_return;
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static void
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sigill_handler (gint n)
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{
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longjmp (sigill_return, 1);
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}
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static gboolean
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arch_accel_sse_os_support (void)
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{
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if (setjmp (sigill_return))
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{
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return FALSE;
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}
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else
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{
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signal (SIGILL, sigill_handler);
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__asm__ __volatile__ ("xorps %xmm0, %xmm0");
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signal (SIGILL, SIG_DFL);
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}
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return TRUE;
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}
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#endif /* USE_SSE */
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static guint32
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arch_accel (void)
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{
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guint32 caps;
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X86Vendor vendor;
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vendor = arch_get_vendor ();
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switch (vendor)
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{
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case ARCH_X86_VENDOR_NONE:
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caps = 0;
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break;
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case ARCH_X86_VENDOR_AMD:
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case ARCH_X86_VENDOR_HYGON:
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caps = arch_accel_amd ();
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break;
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case ARCH_X86_VENDOR_CENTAUR:
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caps = arch_accel_centaur ();
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break;
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case ARCH_X86_VENDOR_CYRIX:
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case ARCH_X86_VENDOR_NSC:
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caps = arch_accel_cyrix ();
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break;
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/* check for what Intel speced, even if UNKNOWN */
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default:
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caps = arch_accel_intel ();
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break;
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}
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#ifdef USE_SSE
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if ((caps & PIKA_CPU_ACCEL_X86_SSE) && !arch_accel_sse_os_support ())
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caps &= ~(PIKA_CPU_ACCEL_X86_SSE | PIKA_CPU_ACCEL_X86_SSE2);
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#endif
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return caps;
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}
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#endif /* ARCH_X86 && USE_MMX && __GNUC__ */
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#if defined(ARCH_PPC) && defined (USE_ALTIVEC)
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#if defined(HAVE_ALTIVEC_SYSCTL)
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#include <sys/sysctl.h>
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#define HAVE_ACCEL 1
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static guint32
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arch_accel (void)
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{
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gint sels[2] = { CTL_HW, HW_VECTORUNIT };
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gboolean has_vu = FALSE;
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gsize length = sizeof(has_vu);
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gint err;
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err = sysctl (sels, 2, &has_vu, &length, NULL, 0);
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if (err == 0 && has_vu)
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return PIKA_CPU_ACCEL_PPC_ALTIVEC;
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return 0;
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}
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#elif defined(__GNUC__)
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#define HAVE_ACCEL 1
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static sigjmp_buf jmpbuf;
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static volatile sig_atomic_t canjump = 0;
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static void
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sigill_handler (gint sig)
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{
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if (!canjump)
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{
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signal (sig, SIG_DFL);
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raise (sig);
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}
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canjump = 0;
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siglongjmp (jmpbuf, 1);
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}
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static guint32
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arch_accel (void)
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{
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signal (SIGILL, sigill_handler);
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if (sigsetjmp (jmpbuf, 1))
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{
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signal (SIGILL, SIG_DFL);
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return 0;
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}
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canjump = 1;
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asm volatile ("mtspr 256, %0\n\t"
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"vand %%v0, %%v0, %%v0"
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:
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: "r" (-1));
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signal (SIGILL, SIG_DFL);
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return PIKA_CPU_ACCEL_PPC_ALTIVEC;
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}
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#endif /* __GNUC__ */
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#endif /* ARCH_PPC && USE_ALTIVEC */
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static PikaCpuAccelFlags
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cpu_accel (void)
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{
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#ifdef HAVE_ACCEL
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static guint32 accel = ~0U;
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if (accel != ~0U)
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return accel;
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accel = arch_accel ();
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return (PikaCpuAccelFlags) accel;
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#else /* !HAVE_ACCEL */
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return PIKA_CPU_ACCEL_NONE;
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#endif
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}
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